The present invention relates to integrated circuits and to methods for manufacturing them.
The present invention is an improvement on the device structure and processes taught in the following application, which is hereby incorporated by reference: Ser. No. 728,961, filed 04/30/85 (TI-10667). The present invention also provides substantial improvements when applied to other non-volatile memory cell architectures, including those which do not use a buried n+ layer.
A key idea of the present invention is that, in the process used to build such devices, the stack etch is immediately followed by (or continued as) a trench etch. That is, after the buried N+ lines under field oxide have been formed, and lines of the first polysilicon (or silicide or polycide) layer (poly 1) have been formed between and parallel to the buried N+ lines, a second polysilicon (or silicide or polycide) layer poly 2 will be deposited. The second polysilicon layer is etched with a stack etch (at least in the array of memory cells--additional patterning steps may be used to modify this sequence for the devices used in the periphery of the memory integrated circuit), and the poly 2 level will now be etched to form wordlines which are substantially orthogonal to the buried N+ bitlines. Moreover, the poly 2 etch will be performed as a stack etch, so that all portions of poly 1 except those which are covered by poly 2 will be etched away. Thus, the poly 1 plates under the poly 2 wordlines will provide the floating gates of FAMOS transistors, providing the capability for operation as a non-volatile memory.
Thus, the stack etch normally patterns more than one layer of material at a time, and will be performed by sequentially changing the flows of etchant gases used. For example, a short initialization step might be used to clear off native oxide from the top surface of the poly 2 layer, and then a silicon etch which was selective to oxide would be used to cut through the poly 2 layer, and then an oxide/nitride etch which was selective to silicon would be used to cut through the interlevel oxide/nitride between poly 1 and poly 2, and then another long silicon etch would be used to cut through the poly 1. With appropriate etch chemistries, this sequence of steps results in a poly 1/oxidenitride dielectric/poly 2 stack wherein the edges of all the layers are neatly aligned, at the desired locations of FAMOS transistors.
One teaching of the present invention is that this stack etch can be prolonged as (or followed by) a trench etch, to give greatly improved results. That is, in the stack etch sequence, after the poly 1 layer has been etched, a further short oxide etching step is used to remove the gate oxide under the poly 1, and a long silicon etch (which must be selective to oxide) is then used to etch a trench into the substrate at the exposed location. That is, after the poly 2 layer has been etched during the stack etch, the oxide/nitride etch which removes the interlevel oxide/nitride will also remove a comparable thickness from the thick oxide over the buried N+ bitlines. However, this oxide is so thick (typically several thousand Angstroms--4500 in the preferred embodiment) that no significant damage will be done to the thick oxide layer during this step. Similarly, during the oxide etch which removes the gate oxide from under the first poly level, the large thickness of the thick oxide over the bitlines will again prevent damage. This thick oxide is also exposed to the silicon etch during the etches which remove poly 1 and which etch into the substrate, but these etches can easily be made so selective to oxide that no significant damage to the thick oxide over the bitlines is incurred.
The masking material used must, of course, be durable enough to withstand the necessary etching duration without loss of linewidth control, but this too is not a practical problem.
Thus the present invention requires only a minimal addition to the existing processing sequence to fabricate the trench isolation between adjacent buried N+ bittlines. However, the advantages which result from the structure thus formed are tremendous. First, as might be expected, the leakage current between adjacent N+ buried bitlines is tremendously reduced, simply because the physical path along which leakage must occur has been greatly elongated. Secondly, the punchthrough voltage between adjacent buried N+ bitlines is also very substantially increased for similar reasons. However, a third very surprising and important advantage has also resulted from this modified processing sequence. It has been found that the cells program much faster using the trench structure taught by the present invention than in the previously developed structure using comparable geometries. The reasons for this are not entirely understood. It is believed that one cause of this effect that the capacitance of poly 1 to substrate has been reduced. That is, a general determinant of programmability is the ratio of the coupling from poly 2 to poly 1 to the coupling from poly 1 to substrate and buried n+. If the coupling of poly 1 to poly 2 can be increased, or the coupling of poly 1 to substrate decreased, signals applied to poly 2 will be able to pull the poly 1 gate over a larger voltage swing, and therefore the voltage differences between poly 1 and substrate, which cause electron injection and therefore programming, will be increased.
Thus, using the present invention, the poly 1 floating gate is still located directly over silicon substrate portions. However, the fringing capacitance at the lower corners of the poly 1 floating gate is significantly reduced (in general, fringing capacitance becomes an increasingly large fraction of the total capacitance of a conductor as the linewidth of the conductor is reduced). That is, this fringing field capacitance portion no longer has a doped silicon semiconductor portion to couple to, but instead there is merely a dielectric (the dielectric which is used to refill the trench isolation) instead of the semiconductor material which would otherwise have been present. Since the fringing field capacitance is reduced, the total coupling of poly 1 to substrate is reduced, and therefore, the relative coupling efficiency between poly 1 and poly 2 is increased, and therefore programmability is increased.
It is believed that a second reason for the very surprising advantage in programmability may be in the way that the diffusion profiles in the substrate are modified by the silicon etch which forms the trench isolation. That is, the N+ buried bitlines will normally have some additional outdiffusion during subsequent stages of processing, and the removal of the silicon material into which they could outdiffuse will necessarily affect the net dopant concentration profiles. Moreover, there may be some segregation of dopants into the deposited dielectric, either during the deposition process or afterward. Thus, the dopant concentration profiles below the buried N+ bitlines are not precisely the same in the present invention as with the structures formerly used. Note that the relevant diffusion profiles are three-dimensional profiles, and three-dimensional modeling must be used to show the full influence of the present invention.
Thus, the present invention provides very significant performance advantages at an absolutely minimal cost of increased processing, and therefore represents a substantial advantage over the crosspoint EPROM cells previously developed.
Thus, the present invention provides at least the following advantages, in addition to others mentioned in this application:
Faster programming PA1 Programming at lower voltages PA1 Higher punchthrough voltage between bitlines PA1 Lower leakage between bitlines.
According to the present invention there is provided: A nonvolatile memory cell array comprising: a semiconductor body; a plurality of bitline diffusions; a plurality of wordlines which are not parallel to said bitline diffusions, said plural wordlines being respectively mutually parallel; a plurality of floating gates underlying said wordlines at locations in between said bitline diffusions, each said floating gate defining a transistor channel location substantially thereunder; a plurality of trenches in said semiconductor body, said trenches separating adjacent ones of said channel locations one from another where said channel locations are not separated by said bitline diffusions.
According to the present invention there is also provided: A non-volatile memory cell array comprising: a semiconductor body; a plurality of substantially parallel bitline insulator strips on said semiconductor body; a plurality of bitline diffusions each underlying on of said bitline insulator strips: a plurality of wordlines which are not parallel to said bitline diffusions, said plural wordlines being respectively mutually substantially parallel: a plurality of floating gates underlying said wordlines at locations in between said bitline diffusions, each said floating gate defining a transistor channel location substantially thereunder; a plurality of trenches in said semiconductor body, said trenches separating adjacent ones of said channel locations one from another where said channel locations are not separated by said bitline diffusions.
According to the present invention there is also provided: A method for fabricating a non-volatile memory array, comprising the steps of: providing a semiconductor body; forming a plurality of bitline diffusions overlaid by bitline insulators near the surface of said semiconductor body; depositing and patterning a first insulated conductive layer to form conductive strips; depositing a second insulated conducting layer; etching said second conductive layer to form wordlines which are not parallel to said bitline diffusions, while also etching away portions of said first conductive layer which do not underlie portions of said second conductive layer and also etching away portions of said semiconductor body which underlie neither portions of said second conductive layer nor portions of said bitline insulator to a depth at least half that of said bitline diffusion.
According to the present invention there is also provided: A method for fabricating a non-volatile memory array, comprising the steps of: providing a semiconductor body; forming a plurality of bitline diffusions near the surface of said semiconductor body; depositing and patterning a first insulated conductive layer to form conductive strips; depositing a second insulated conductive layer; etching said second conductive layer to form wordlines which are not parallel to said bitline diffusions, while also etching away portions of said first conductive layer which do not underlie portions of said second conductive layer and also etching away portions of said semiconductor body which underlie neither portions of said second conductive layer nor portions of said bitline insulator to a depth at least 25% that of said bitline diffusion.